RTL v1.1 · Spec v1.1 · DUT bugs closed

CPM UVM verification

UVM environment for the Configurable Packet Modifier (CPM): dual agents, RAL, SVA on interfaces, functional coverage, scoreboard, and reference model. Three DUT bugs found in verification, fixed in RTL v1.1; regression clean with spec v1.1.

505
Packets Tested
0
Mismatches
100%
Coverage
0
SVA Violations
3
Bugs Found & Fixed

DUT Overview

The Configurable Packet Modifier (CPM) is a hardware IP block that processes streaming packets with configurable transformations.

Operation Modes

0
PASS
payload unchanged
0 cycles
1
XOR
payload ^ MASK
1 cycle
2
ADD
payload + ADD_CONST
2 cycles
3
ROT
rotate left by 4
1 cycle

Register Map

Address Name Access Fields Description
0x00 CTRL RW ENABLE[0], SOFT_RST[1] Control register
0x04 MODE RW MODE[1:0] Processing mode (0-3)
0x08 PARAMS RW MASK[15:0], ADD_CONST[31:16] Mode parameters
0x0C DROP_CFG RW DROP_EN[0], DROP_OPCODE[7:4] Drop configuration
0x10 STATUS RO BUSY[0] Pipeline busy status
0x14 COUNT_IN RO [31:0] Input packet counter
0x18 COUNT_OUT RO [31:0] Output packet counter
0x1C DROPPED_COUNT RO [31:0] Dropped packet counter
Critical Invariant

COUNT_OUT + DROPPED_COUNT == COUNT_IN
This invariant must always hold when the pipeline is stable (STATUS.BUSY = 0). The verification environment checks this at end-of-test via RAL readback.

Specification Requirements

Mandatory requirements from the verification project specification. All must be implemented for closure.

Mandatory UVM Mechanisms

1. RAL (Register Abstraction Layer)
MANDATORY
  • CpmRegModel with all 8 registers
  • CpmRegAdapter for bus conversion
  • uvm_reg_predictor for auto-prediction
  • uvm_reg_hw_reset_seq executed
  • CpmConfigSeq for RAL-based configuration
2. Virtual Sequence
MANDATORY
  • CpmTopVirtualSeq orchestrates complete flow
  • 8-step flow: Reset, Configure, Traffic, Reconfigure, Stress, Drop, Readback, End
  • Raises/drops objections at virtual sequence level
3. Factory Override
MANDATORY
  • CpmBaseTrafficSeq overridden by CpmCoverageTrafficSeq
  • Applied in CpmMainTest.build_phase()
  • Demonstrates polymorphism
4. Callbacks
MANDATORY - NEW
  • CpmPacketStatsCb with real purpose
  • Tracks packet statistics (opcode count, payload range)
  • Registered in CpmMainTest.connect_phase()
5. Functional Coverage
MANDATORY
  • MODE: 100% (all 4 modes)
  • OPCODE: 100% (all 16 opcodes)
  • MODE x OPCODE Cross: 100% (64 bins)
  • Drop/Stall bins: 50% (hit at least once)
6. SVA Assertions
MANDATORY
  • p_input_stability - Input stable under stall
  • p_output_stability - Output stable under stall
  • p_bounded_liveness - Packet out within latency
  • 4 cover properties - All hit

Coverage Plan

Functional and code coverage strategy to verify all DUT features are exercised.

Functional Coverage Strategy

The coverage model is implemented in CpmPacketCoverage.sv and CpmRegCoverage.sv using SystemVerilog covergroups.

Coverpoint Description Target Rationale
cp_mode All 4 operation modes (PASS, XOR, ADD, ROT) 100% Each mode has unique transformation logic that must be verified
cp_opcode All 16 opcode values (0x0-0xF) 90% Opcodes interact with drop mechanism; high coverage ensures corner cases
cp_mode_opcode Cross coverage: MODE x OPCODE (64 bins) 80% Ensures all mode/opcode combinations are tested
cp_drop Drop event occurrence (drop_hit, no_drop) Hit once Verify drop mechanism is exercised during testing
cp_stall Backpressure/stall events (stall_hit, no_stall) Hit once Verify pipeline backpressure scenarios are tested

Code Coverage Targets

Code coverage is collected on the DUT (cpm_rtl.sv) using QuestaSim's built-in coverage tools.

Metric Target Description
Statements 95% Percentage of executable statements exercised
Branches 90% Percentage of if/else and case branches taken
Expressions 90% Boolean sub-expression coverage
Conditions 80% Individual condition outcomes in expressions
Toggles 50% Signal toggle activity (0→1 and 1→0)

Register Coverage

Register coverage is collected in CpmRegCoverage.sv to ensure all register access patterns are exercised.

Assertions Plan

SystemVerilog Assertions (SVA) to verify protocol compliance and DUT behavior at the RTL level.

Assertions are implemented in CpmStreamIf.sv and monitor the streaming interface protocol. All assertions are disabled during reset (disable iff (rst)) to avoid false failures.

Planned Assertions

Assertion Requirement Description
p_input_stability Spec 6.3 When input is valid but not ready (stall condition), all input signals (ID, opcode, payload) must remain stable on the next clock cycle. This ensures the DUT properly handles backpressure from downstream.
p_output_stability Spec 6.3 When output is valid but not ready (output stall), all output signals must remain stable on the next clock cycle. This verifies the DUT holds output data during backpressure.
p_bounded_liveness Spec 4.1-4.4 When a packet is accepted at input and output is ready, a packet must exit within a bounded number of cycles (10 cycles to allow for pipeline latency). Disabled when packet is expected to be dropped.

Planned Cover Properties

Cover properties ensure that important protocol scenarios are exercised during simulation:

Cover Property Purpose
c_input_stall Verify that input stall events (in_valid high, in_ready low) occur during testing
c_output_stall Verify that output stall events (out_valid high, out_ready low) occur during testing
c_in_fire Verify that input handshakes (in_valid AND in_ready) complete successfully
c_out_fire Verify that output handshakes (out_valid AND out_ready) complete successfully

Verification Environment Architecture

Dual-agent UVM architecture with complete separation between packet processing and register configuration.

tb_top.sv

Testbench Top Module - Hardware Level

Clock (100MHz)
Reset Generation
uvm_config_db
run_test()
CpmStreamIf
Stream Interface + SVA
4 SVA Assertions:
  • Input stability
  • Output stability
  • Bounded liveness
  • 4 Cover properties
CpmRegIf
Register Bus Interface
Signals:
  • req, gnt
  • addr, wdata, rdata
  • write_en
CPM DUT
cpm_rtl.sv (v1.1)
BUGS FIXED
RTL v1.1
Virtual interfaces passed via uvm_config_db#(virtual CpmStreamIf/CpmRegIf)::set
|
v
CpmEnv

UVM Environment (inside Test)

CpmPacketAgent
Stream Interface
CpmPacketDriver
  • Valid/Ready handshake
  • Callback hooks (pre/post_drive)
CpmPacketSequencer
CpmPacketMonitor
  • Dual ports: m_ap_input, m_ap_output
  • Latency tracking
CpmRegAgent
Register Bus
CpmRegDriver
  • Req/Gnt protocol
  • Read/Write ops
CpmRegSequencer
CpmRegMonitor
  • Transaction extraction
  • m_ap → Predictor
CpmScoreboard
Checking
CpmRefModel
  • 4 operation modes
  • Drop logic
Compare Logic
  • Expected queue
  • ID+Opcode match
CpmPacketCoverage
  • MODE 100%
  • OPCODE 100%
  • Cross 100%
  • Drop/Stall 50%
CpmRegCoverage
  • Address 100%
  • Operation 100%
  • Cross 75%
CpmRegModel (RAL)
  • 8 Registers
  • CpmRegAdapter
  • uvm_reg_predictor

TLM Connections

Source Destination Purpose
PacketMonitor.m_ap_input Scoreboard.write_input() Send input packets for expected queue
PacketMonitor.m_ap_output Scoreboard.write_output() Send output packets for comparison
PacketMonitor.m_ap_input PacketCoverage.write() Collect functional coverage
RegMonitor.m_ap uvm_reg_predictor.write() RAL prediction
RegMonitor.m_ap RegCoverage.write() Register coverage

UVM Component Hierarchy

Complete UVM component hierarchy showing the relationship between all verification components.

Component Tree

Note: Replace this auto-generated diagram with your original hand-drawn component tree diagram for the final presentation.

uvm_test_top
CpmMainTest | CpmSmokeTest | CpmRalResetTest
m_env (CpmEnv)
m_packet_agent
m_sequencer
m_driver + Callbacks
m_monitor
m_ap_input, m_ap_output
m_reg_agent
m_sequencer
m_driver
m_monitor
m_ap (to Predictor)
m_scoreboard
  • CpmRefModel
  • Expected queue
  • write_input/output()
Coverage
  • m_packet_coverage
  • m_reg_coverage
RAL
  • m_reg_model (8 regs)
  • m_reg_adapter
  • m_predictor
Virtual Sequences
Started on m_env.m_packet_agent.m_sequencer
CpmTopVirtualSeq CpmConfigSeq CpmBaseTrafficSeq CpmStressSeq CpmDropSeq

Component Statistics

2
Agents
4
Monitors
8
Registers
6
Sequences
4
Tests

RAL Model

Register Abstraction Layer (RAL) implementation - mandatory requirement for systematic register verification.

CpmRegModel
Register Block

Central register model containing all 8 CPM registers with proper field definitions.

RegisterAccessFields
m_ctrlRWm_enable, m_soft_rst
m_modeRWm_op_mode
m_paramsRWm_mask, m_add_const
m_drop_cfgRWm_drop_en, m_drop_opcode
m_statusROm_busy
m_count_inROm_count_in
m_count_outROm_count_out
m_dropped_countROm_dropped_count
RAL Flow
Read/Write Path
CpmConfigSeq
RAL API
→
CpmRegModel
Mirror
→
Adapter
reg2bus()
↓
Predictor
Auto-update
←
CpmRegDriver
Bus xfer
↑
Updates mirror

RAL Reset Sequence

Mandatory Reset Verification

CpmRalResetTest executes the built-in UVM reset verification sequence to confirm all register reset values match the specification. This is a mandatory requirement per the verification deliverables document.

Sequence Library

Complete sequence library with virtual sequences orchestrating the test flow.

Virtual Sequence Flow

1
Reset Wait
Wait for reset deassert
2
Configure
CpmConfigSeq via RAL
3
Traffic
200 random packets
4
Reconfigure
Cycle all 4 modes
5
Stress
Burst traffic (20/burst)
6
Drop Test
20 dropped packets
7
Readback
RAL counter check
8
End Check
Verify invariant
CpmTopVirtualSeq (MANDATORY)
  • Raises objection at start, drops at end
  • Checks counter invariant via RAL when STATUS.BUSY == 0
  • Waits for pipeline drain before final checks

Sequence Types

Virtual Sequences
Orchestration layer
  • CpmTopVirtualSeq - Main test flow
  • 8-step orchestration
  • Raises/drops objections
  • Counter invariant check
RAL Sequences
Configuration layer
  • CpmConfigSeq - Programs registers
  • Sets MODE, MASK, ADD_CONST
  • Configures DROP_EN, DROP_OPCODE
  • Uses RAL API for all writes
Packet Sequences
Traffic layer
  • CpmBaseTrafficSeq - Random packets
  • CpmStressSeq - Burst traffic
  • CpmDropSeq - Target drop opcode
  • CpmCoverageTrafficSeq - All 16 opcodes

Factory Override

The factory override mechanism allows dynamic substitution of sequence types at runtime. In CpmMainTest.build_phase(), the base traffic sequence is overridden with a coverage-driven variant (CpmCoverageTrafficSeq) to ensure all opcodes are exercised.

Callback Implementation

Mandatory callback mechanism implemented with real purpose: tracking packet statistics throughout simulation.

The callback mechanism allows external observers to hook into the packet driver's execution flow without modifying the driver itself. This project implements CpmPacketStatsCb, a concrete callback that collects statistics during simulation.

CpmPacketStatsCb
Packet Statistics Callback

Extends CpmBasePacketCb with real statistics tracking functionality:

  • Opcode distribution: Count per opcode (0-15)
  • Total packets: Number of packets driven
  • Payload range: Min/max payload values
  • Timing: First and last packet timestamps
Callback Results
From CpmMainTest
Packet Callback Statistics:
  Total packets: 505
  Opcodes used: 16/16
  Payload range: 0x0000 - 0xFFFF
  Duration: 465ns - 169.3ms

Registration: Callback is registered in CpmMainTest.connect_phase() using the UVM callback API.

Verification Results Summary

Complete verification results demonstrating all closure criteria have been met with RTL v1.1.

Test Results

Test Packets Matched Dropped Mismatched Status
CpmSmokeTest 10 10 0 0 PASS
CpmMainTest 505 485 20 0 PASS
CpmRalResetTest N/A N/A N/A N/A PASS

Key Metrics

505
Packets Input
All processed
485
Packets Output
All matched
20
Dropped
Intentional
0
Mismatches
100% accuracy
0
Errors
Clean run

Functional Coverage Results

100%
MODE Coverage
Target: 100%
100%
OPCODE Coverage
Target: 90%
100%
MODE x OPCODE Cross
Target: 80%
50%
Drop/Stall Bins
Target: Hit once

Code Coverage Results (DUT)

Metric Coverage Target Status
Statements 100.00% 95% Exceeds
Branches 95.55% 90% Exceeds
Expressions 100.00% 90% Exceeds
Conditions 88.88% 80% Exceeds
Toggles 58.62% 50% Exceeds
Total DUT 88.61% 85% Exceeds

Assertion Results

SVA Assertion Status

Assertion Status
p_input_stability PASS
p_output_stability PASS
p_bounded_liveness PASS

Assertion Summary

3/3
Assertions Pass
0
Violations
4
Cover Properties
100%
Cover Hits

Counter Invariant Verification

Counter Invariant PASS

COUNT_IN (40) == COUNT_OUT (40) + DROPPED_COUNT (0)

Verified via RAL readback after waiting for STATUS.BUSY == 0.
RTL v1.1 fix confirmed: counters now correct under backpressure.

Closure Criteria Checklist

  • All tests pass (no runtime hangs)
  • Scoreboard reports 0 mismatches
  • All 3 SVA assertions pass (0 violations)
  • Functional coverage targets achieved
  • RAL reset sequence passes cleanly
  • Counter invariant verified via RAL
  • UVM_ERROR count = 0
  • All 4 operation modes verified
  • Factory override demonstrated
  • Callback with real purpose (CpmPacketStatsCb)
  • Virtual sequence orchestrates complete flow
  • All DUT bugs fixed in RTL v1.1
  • Spec v1.1 compliance verified
  • Documentation complete

Bug Tracking and Resolution

Complete history of discovered bugs, their root causes, and resolutions. All DUT bugs have been fixed in RTL v1.1.

DUT Bugs (All Fixed in RTL v1.1)

DUT-001
COUNT_OUT Over-Count Bug
[FIXED]

Issue: Counter incremented on out_valid instead of out_fire, causing multiple counts per packet during backpressure.

Fix: Changed line 287 from if(out_valid) to if(out_fire)

DUT-002
Output Stability Violation
[FIXED]

Issue: Output signals changed while out_valid=1 and out_ready=0, violating Spec Section 6.3 stability rules.

Fix: s0 slot only updates on out_fire

DUT-003
ROT_AMT Not Configurable
[RESOLVED]

Issue: ROT_AMT hardcoded as localparam instead of configurable register.

Resolution: Spec v1.1 clarifies ROT_AMT is intentionally fixed at 4 bits (not a bug)

Testbench Bugs (All Closed)

Bug ID Title Severity Status Resolution
TB-001 Virtual Interface config_db Collision Critical Closed Direct uvm_config_db::set for each interface type
TB-002 Reset Wait Race Condition High Closed Changed to clocked wait: do @(posedge clk) while (rst)
TB-003 Zero-Time Loop in Monitor High Closed Added clock edge before task calls
TB-004 Reference Model Config Stale Medium Closed Read config from RAL model in predict_output()
TB-005 Scoreboard FIFO Ordering Assumption Medium Closed Match by ID+OPCODE instead of FIFO order
TB-006 RAL Model Not Built Critical Closed Added m_reg_model.build() in CpmEnv

Spec Ambiguities Status

Issue Status Resolution
ROT_AMT value undefined Resolved Spec v1.1 confirms fixed at 4 bits
Counter invariant timing Resolved STATUS.BUSY defines when invariant holds
SOFT_RST scope Resolved "Clears counters and internal state" includes pipeline
Ordering contradiction Open Different latencies vs "no reordering" - needs clarification
Counter overflow behavior Open Standard wrap assumed (low priority)

Repository file structure

Paths match the Git tree (verification/, cpm_design/). The bench contains 50 SystemVerilog files under verification/, plus RTL and scripts documented below.

RTL

PathPurpose
cpm_design/cpm_rtl.sv CPM DUT

Packages (verification/pkg/) — 11 files

PathPurpose
verification/pkg/CpmParamsPkg.svParameters, field widths, cpm_mode_e, map constants
verification/pkg/CpmTransactionsPkg.svPacket and register transactions
verification/pkg/CpmConfigPkg.svEnv and agent configuration types
verification/pkg/CpmRalPkg.svRAL package / includes
verification/pkg/CpmPacketAgentPkg.svPacket agent compilation unit
verification/pkg/CpmRegAgentPkg.svRegister agent compilation unit
verification/pkg/CpmCoveragePkg.svFunctional coverage
verification/pkg/CpmScoreboardPkg.svScoreboard and reference model
verification/pkg/CpmSequencesPkg.svSequences
verification/pkg/CpmTestsPkg.svTests
verification/pkg/CpmEnvPkg.svTop environment package

Transactions — 2 files

PathPurpose
verification/transactions/CpmPacketTxn.svStream packet item
verification/transactions/CpmRegTxn.svRegister bus item

Interfaces — 2 files

PathPurpose
verification/interfaces/CpmStreamIf.svStream valid/ready, SVA and cover properties
verification/interfaces/CpmRegIf.svRegister bus signals

Configuration — 3 files

PathPurpose
verification/config/CpmStreamAgentConfig.svPacket agent config
verification/config/CpmRegAgentConfig.svRegister agent config
verification/config/CpmEnvConfig.svEnvironment config

Packet agent — 4 files (verification/agent/packet/)

PathPurpose
verification/agent/packet/CpmPacketDriver.svValid/ready driver, callback hooks
verification/agent/packet/CpmPacketMonitor.svDual analysis ports (in/out)
verification/agent/packet/CpmPacketSequencer.svPacket sequencer
verification/agent/packet/CpmPacketAgent.svAgent

Register agent — 4 files (verification/agent/reg/)

PathPurpose
verification/agent/reg/CpmRegDriver.svReq/gnt protocol
verification/agent/reg/CpmRegMonitor.svBus observer for RAL / coverage
verification/agent/reg/CpmRegSequencer.svReg sequencer
verification/agent/reg/CpmRegAgent.svAgent

RAL — 3 files

PathPurpose
verification/ral/CpmRegModel.svEight registers (CTRL, MODE, PARAMS, DROP_CFG, STATUS, counters)
verification/ral/CpmRegAdapter.svreg2bus / bus2reg
verification/ral/CpmRegPredictor.svuvm_reg_predictor

Sequences — 6 files

PathPurpose
verification/sequences/virtual/CpmTopVirtualSeq.svTop virtual sequence (full flow)
verification/sequences/ral/CpmConfigSeq.svRAL programming
verification/sequences/packet/CpmBaseTrafficSeq.svBase random traffic
verification/sequences/packet/CpmStressSeq.svBurst stress
verification/sequences/packet/CpmDropSeq.svDrop-oriented stimulus
verification/sequences/packet/CpmCoverageTrafficSeq.svCoverage / opcode sweep

Scoreboard — 4 files

PathPurpose
verification/scoreboard/CpmScoreboard.svMain scoreboard, queues, invariants
verification/scoreboard/CpmRefModel.svReference model (modes, drop, latency)
verification/scoreboard/CpmScoreboardOutputImp.svOutput analysis_imp
verification/scoreboard/CpmScoreboardModeImp.svMode side-band analysis_imp

Coverage — 2 files

PathPurpose
verification/coverage/CpmPacketCoverage.svPacket / mode / cross / stall / drop
verification/coverage/CpmRegCoverage.svRegister access coverage

Callbacks — 3 files

PathPurpose
verification/callbacks/CpmBasePacketCb.svBase packet callback; includes class CpmPacketStatsCb (same file, not a separate .sv)
verification/callbacks/CpmBaseRegCb.svBase register callback
verification/callbacks/CpmBaseMonitorCb.svBase monitor callback

Tests — 4 files

PathPurpose
verification/tests/CpmBaseTest.svCommon test base
verification/tests/CpmMainTest.svPrimary test: virtual seq, factory override, stats callback
verification/tests/CpmSmokeTest.svSmoke
verification/tests/CpmRalResetTest.svRAL hardware reset

Environment and testbench top

PathPurpose
verification/env/CpmEnv.svTop UVM env: agents, scoreboard, coverage, RAL, TLM
verification/tb_top.svDUT, interfaces, clocks, reset, run_test()

Scripts (simulation)

PathPurpose
scripts/Run/run.pyTest runner
scripts/Run/compile.doQuesta compile
scripts/Run/elaborate.doQuesta elaborate
scripts/Run/assertion_report.doAssertion report
scripts/generate_coverage_report.pyOptional coverage HTML

Canonical listing: docs/FILE_STRUCTURE.md (same content as this section).

Project Phases

The verification project was executed in 13 phases, each with specific deliverables.

01
Project Setup & Architecture
Established the verification/ tree (50 SystemVerilog files), package layering, dual-agent architecture, RAL integration, and virtual sequence flow.
02
Transaction & Interface Layer
Implemented CpmPacketTxn and CpmRegTxn with do_copy, do_compare, constraints. Created CpmStreamIf and CpmRegIf interfaces with SVA assertions.
03
Driver & Sequencer Layer
Built CpmPacketDriver with valid/ready protocol, CpmRegDriver with req/gnt protocol. Added callback hooks and reset handling.
04
Monitor & Coverage Layer
Created monitors for both interfaces. Implemented CpmPacketCoverage with all mandatory coverpoints (MODE, OPCODE, Cross, Drop, Stall).
05
Agent & Environment Layer
Built CpmPacketAgent and CpmRegAgent with active/passive modes. Created CpmEnv with all TLM connections and component integration.
06
Sequence Library & RAL
Implemented RAL model with all 8 registers, adapter, predictor. Created virtual sequence with 8-step flow and leaf sequences (traffic, stress, drop, coverage).
07
Scoreboard & Checkers
Built scoreboard with reference model implementing all 4 modes. Added expected queue, comparison logic, mismatch reporting, and end-of-test checks.
08
Callbacks & Extensions
Created CpmBasePacketCb, CpmBaseRegCb, CpmBaseMonitorCb with pre/post hooks. Implemented CpmPacketStatsCb with real statistics tracking.
09
Test Suite Development
Created CpmBaseTest, CpmMainTest (with factory override & callback), CpmSmokeTest, and CpmRalResetTest (mandatory RAL reset verification).
10
Testbench Top & Simulation
Created tb_top.sv with DUT instantiation, clock/reset generation, virtual interface connections. Built compile.do, elaborate.do, and run.py scripts.
11
Verification & Debugging
Fixed compilation errors, debugged crashes, resolved race conditions. Found and documented 3 DUT bugs (all fixed in RTL v1.1).
12
Documentation & Deliverables
Created VERIFICATION_PLAN.md, TEST_SUITE.md, USER_GUIDE.md, TROUBLESHOOTING.md, SIGNOFF.md. Built modern HTML coverage report generator.
13
RTL v1.1 & Sign-Off
Verified RTL v1.1 bug fixes. Updated all tracking files. Achieved 0 errors, 0 SVA violations. Complete sign-off with spec v1.1 compliance.

What's New in v1.1

Major updates since the initial release, including RTL bug fixes, new callback implementation, and spec clarifications.

RTL Bugs Fixed
RTL v1.1
  • COUNT_OUT: Now increments on out_fire
  • Output Stability: Signals stable during stall
  • ROT_AMT: Fixed at 4 bits (per spec)
Callback Implementation
CpmPacketStatsCb
  • Tracks packet statistics in real-time
  • Counts packets per opcode (16 bins)
  • Records min/max payload values
  • Measures test duration
Spec v1.1 Compliance
All clarifications addressed
  • ROT_AMT: Fixed at 4 bits
  • STATUS.BUSY: Defines invariant timing
  • SOFT_RST: Clears internal state
Clean Simulation Results

UVM_ERROR: 0 | SVA Violations: 0 | Mismatches: 0
All 505 packets processed correctly. Counter invariant verified via RAL. All 4 SVA assertions pass.